A 3.2-GHz 405 fs_rms Jitter –237.2 dB FoM_JIT Ring-Based Fractional-N Synthesizer

A ring-oscillator (RO)-based low-jitter digital fractional-N frequency synthesizer is presented. It employs a doubler (FD) that doubles the reference clock frequency, 2-bit time-to-digital converter (TDC) with optimized thresholds to minimize quantization error, and high-resolution digital-to-time (DTC) cancel error of delta-sigma fractional divider (FDIV). DTC’s linearity improved using piecewise linear (PWL) function-based correction scheme. On-chip calibration extensively used correct imperfections FD, TDC, DTC. prototype incorporating proposed techniques implemented in 65-nm CMOS produces 3.2-GHz output from 96-MHz input clock. The worst-case integrated jitter 306 405 fs integer modes, respectively. consumes 11.7 mW 1-V supply which 7.84 consumed by oscillator. figure-of-merit −237.2 dB.